The present technique relates to terminal structures and power electronic devices and their incorporation into modules and systems. More particularly, the technique relates to an improved terminal assembly that significantly reduces parasitic inductance and inherently provides for cooling and interfacing of circuits and power electronic devices.
A wide array of applications are known for power electronic devices, such as power switches, transistors, and the like. For example, in industrial applications, silicon controlled rectifiers (SCRs), insulated gate bipolar transistors (IGBTs), field effect transistors (FETs), and so forth are used to provide power to loads. In certain applications, for example, arrays of power switches are employed to convert direct current power to alternating current waveforms for application to loads. Such applications include motor drives. However, many more applications exist for inverter circuitry and other circuitry incorporating such devices. Other settings include electric vehicle applications grid tie inverters, DC to DC converters, AC to AC power Converters, and many other solid state power conversion elements that require a packaged power device switch topology. In electric vehicles, a source of direct current is typically available from a battery or power supply system incorporating a battery or other direct or rotating energy converter. Power electronic devices are employed to convert this power to alternating current waveforms for driving one or more electric motors. The motors serve to drive power transmission elements to propel the vehicle. While numerous constraints exist in such settings which differ from those of industrial settings, numerous problems and difficulties are shared in all such applications.
Demands made on power electronic devices typically include their reliability, power output, size and weight limits, and requirements regarding the environmental conditions under which they must operate. Where size and weight constraints force reductions in the packaging dimensions, difficulties arise in appropriately placing the power electronic devices, and drive and control circuitry associated with the devices to sufficiently remove heat generated during their operation. Where size, cost and weight are less important, large heat sinks and heat dissipation devices may be employed utilizing any fluid that can be accommodated by choice of materials that are compatible. However, as packaging sizes are reduced, more efficient and effective techniques are needed. Electrical and electronic constraints also impose difficulties on package design. For example, reduction of inductance in the circuits and circuit layout is commonly a goal, while solutions for reducing inductance may be difficult to realize. Shielding from electromagnetic interference originating both within the package and outside the package may be important, depending upon the surrounding environment. Similarly, appropriate interfacing with external circuitry, and the facility to install, service and replace power electronics packages may be important in certain applications. It has typically been necessary in many instances to configure the power electronic element to match closely the specific needs of the application and by doing so meet cost, size, performance targets that can be achieved by no other means. Finally, certain environments, such as vehicle environments, impose a wide range of difficult operating conditions, including large temperature spans, vibration and shock loading, and so forth.
Another problem in packaging of power electronics circuits is the occurrence of parasitic inductance arising in bus structures. In particular, DC busses are commonly employed in circuits, particularly inverter and converter circuits, for transmitting power, either received in DC form or rectified from AC waveforms. The DC power is typically communicated between energy storage devices, such as capacitors, or rectifiers and switches used to produce controlled frequency AC power. The bus structures can give rise to significant parasitic inductance which adversely affects the performance of the circuitry, and which can ultimately lead to degradation in certain circuit components over time. While numerous attempts have been made to control parasitic inductance, and other adverse affects of the use of extended DC busses, these are often not well adapted to particular structures, depending upon the layout of the packaging.
There is a need, therefore, for improved arrangements for leading power into and away from power electronics and similar circuitry that minimizes the drawbacks of prior art arrangements. In particular, there is a need for terminal structures which reduce the incidence of parasitic inductance, and which, to the extent possible, do away with the need for a DC bus structure.